MNEMONICS | HEX CODE | MNEMONICS | HEX CODE |
MOV [SI], CX | 89 0C | INC AX | 40 |
MOV [SI], DX | 8914 | INC BX | 43 |
MOV SI, 0200H | BE 00 20 | INC CX | 41 |
MOV DI, 0200H | BF 00 20 | INC DX | 42 |
MOV AX, [DI] | 8B 05 | INC SI | 46 |
MOV BX, [DI] | 8B 1D | INC DI | 47 |
MOV CX, [DI] | 8B 0D | DEC AL | FE C8 |
MOV DX, [DI] | 8B 15 | DEC BL | FE CB |
MOV [DI], AX | 89 05 | DEC CL | FE C9 |
MOV [DI], BX | 89 1D | DEC DL | FE CA |
MOV [DI], CX | 89 0D | DEC AH | FE CC |
MOV [DI], DX | 89 15 | DEC BH | FE CF |
MOV AX, 2001 | B8 01 20 | DEC CH | FE CD |
MOV BX, 2001 | BB 01 20 | DEC DH | FECE |
MOV [2001], AX | A3 01 20 | DEC AX | 48 |
MOV [2001], BX | 89 1E 0120 | DEC BX | 4B |
MOV [2001], CX | 89 0E 0120 | DEC CX | 49 |
MOV [2001], DX | 89 16 0120 | DEC DX | 4A |
MOV [2001], SI | 89 36 0120 | DEC SI | 4E |
MOV [2001], DI | 89 3E 0120 | DEC DI | 4F |
INC AL | FE C0 | MOV CX,16 bit | B9 04 00 |
INC BL | FE C3 | MOV SI, 16 bit | BE 00 30 |
INC CL | FE C1 | MOV DI, 16 bit | BF 16 bit |
INC DL | FE C2 | MOV AX [SI] | 8B 04 |
INC AH | FC C4 | ADC [DI], AX | 11 05 |
INC BH | FC C7 | MOV AH,00 | B4 00 |
INC CH | FC C5 | MOV AH[SI] | 8A 24 |
INC DH | FC C6 | MOV [SI],AH | 88 24 |
MNEMONICS | HEX CODE | MNEMONICS | HEX CODE |
MOV BX [SI] | 8B 1C | JNZ | 75 EB |
MOV CX [SI] | 8B 0C | LODSB | AC |
MOV AL, [SI] | 8A 04 | ADD | 03 C3 |
MOV [SI], AL | 88 04 | STOSB | AA |
MOV CX, 0008 | B9 08 00 | DIV DL | F6 F2 |
MOV [DI],00 | C6 05 00 | LOOP NZ | E0 F5 |
MOV [DI],AL | 88 05 | HLT | F4 |
MOV BL,AL | 8A D8 | MUL DL | F6 E2 |
MOV DL,34 | B2 34 | NEG AL | F6 D8 |
MOV DL,36 | B2 34 | STD | FD |
MOV DI,0308 | BF 08 03 | REPNE MOV SW | F2 A5 |
MOV CX,FFFF | B9 FF FF | XLAT | D7 |
MOV AL,03 | B0 03 | MOV CL,04 | B1 04 |
MOV BX,0300 | BB 00 03 | MOV AX[SI] | 8B 04 |
INC CL | FE C1 | MOV BX[SI] | 8B 1C |
MOV [DI],CL | 89 0D | JNC L1 | 73 02 |
MUL BX | F7 E3 | DEC CL | FE C9 |
MOV [DI],AL | 88 05 | MOV [DI],DX | 89 15 |
CMP AL[SI] | 3A 04 | MOV AL,[SI] | 8A 04 |
MOV [DI],AX | 89 05 | MOV BX,AX | 8B D8 |
XCHG AL[SI] | 86 04 | MOV CX[SI] | 8B 0C |
LOOP | E2 F1 | MOV [SI],AL | 88 04 |
MOV CL 00 | B1 00 | MOV AL,83 | B0 83 |
MOV DX,FFFE | BA FE FF | ||
CMP AL,80 | 3C 80 | ||
Most Important Question for Exam
1. The mnemonic that is placed before the arithmetic operation is performed is
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.
2. The Carry flag is undefined after performing the operation
Explanation: Since the operation, AAD is performed before division operation is performed, the carry flag, auxiliary flag and overflow flag are undefined.
3. The instruction that performs logical AND operation and the result of the operation is not available is
Explanation: In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are affected
4. In the RCL instruction, the contents of the destination operand undergo function as
Explanation: In RRTC(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag.
5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX becomes zero, the execution proceeds to the next instruction in sequence.
6. The instructions that are used to call a subroutine from the main program and return to the main program after execution of called function are
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.
7. instruction that unconditionally transfers the control of execution to the specified address is
Explanation: In this the control transfers to the address specified in the instruction and flags are not affected by this instruction.
8. The assembler directives which are the hints using some predefined alphabetical strings are given to
Explanation: These directives help the assembler to correctly understand the assembly language programs to prepare the codes.
9. The logic required for implementing a program can be expressed in terms of
Explanation: The logic required for implementing a program must be visualized clearly which is possible by flowchart and algorithm.
10. The operands, source and destination in an instruction cannot be
Explanation: Only one memory operand can be specified in one instruction
11. The instruction that is not possible among the following is
Explanation: Both the operands cannot be memory operands
12. Both the operands source and destination of an instruction cannot be
Explanation: Since destination operand should not be immediate data.
13. The registers that cannot be used as operands for arithmetic and logical instructions are
Explanation: Segment registers are not allowed as operands for arithmetic and logical instructions.
14. The operands of an instruction cannot be
Explanation: Both the operands should not be immediate operands and memory operands
15. If the processor is executing the main program that calls a subroutine, then after executing the main program up to the CALL instruction, the control will be transferred to
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is transferred to the subroutine address
16. The stack is useful for
Explanation: Stack is used for temporary storage of contents of registers and memory locations, status of registers.
17. The Stack is accessed using
Explanation: The stack is accessed using a pointer that is implemented using SP and SS registers.
18. As the storing of data words onto the stack is increased, the stack pointer is
Explanation: The data is stored from top address of the stack and is decremented by 2.
19. While retrieving data from the stack, the stack pointer is
Explanation: The data in the stack, may again be transferred back from a stack to register. At that time, the stack pointer is incremented by 2.
20. The stack pointer register contains
Explanation: The stack pointer register contains the offset of the address of the stack segment.
21. PUSH operation
Explanation: Each PUSH operation decrements the SP (Stack Pointer) register.
22. The register or memory location that is pushed into the stack at the end must be
Explanation: The data can be retrieved by POP operation and as in stack; the data that is pushed at the end must be popped off first.
23. . In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK the ASSUME directive directs to the assembler the
Explanation: The directive ASSUMES facilitates to name the segments with the desired name that is not a mnemonic or keyword.
24. 8086 does not support
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
25. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
26. If an interrupt is generated from outside the processor then it is an
Explanation: If an external device or a signal interrupts the processor from outside then it is an external interrupt.
27. Example of an external interrupt is
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
28. The type of the interrupt may be passed to the interrupt structure of CPU from
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.
29. During the execution of an interrupt, the data pushed into the stack is the content of
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
30. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called
Explanation: By programming the bits of control word register, the operations of the ports are specified.
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